The present disclosure relates to a circuit for controlling the pulse width of an auto-refresh signal and a circuit for generating an internal row address for auto refresh, and more particularly to circuits for controlling the pulse width of an auto-refresh signal and generating an internal row address for auto refresh, which enable auto refresh to be normally carried out in both high-speed and low-speed operations of a DRAM.
In the current information age, electronic devices are regularly used to store, process, display and otherwise output data in a form useful to us. The data can be stored in any of various structures.
For example, data can be stored, in the form of charge, in an isolated cell capacitor. Since the structure of the cell capacitor is imperfect, the stored charge may be externally leaked due to leakage current. Accordingly, it is necessary to repeatedly perform a procedure for reading the stored data before the data disappears completely, amplifying the read data, and writing the amplified data. This procedure is called a “refresh operation”.
Such a refresh operation may be divided into self refresh and auto refresh. In the self refresh, all memory cells are refreshed in accordance with one command input. On the other hand, in the auto refresh, it is necessary to input a refresh command every time a refresh operation is required.
An auto-refresh operation is carried out in response to an enable state of an auto-refresh signal (such as AREFP6 in FIG. 9(a)) which is enabled in accordance with a combination of a plurality of external command signals (such as cas, ras, we, and cs). However, when the enable period of the auto-refresh signal is excessively short, a flag signal (such as INTAXP16 in FIG. 9(c)) may disappear during a high-speed operation (for example, tck=1 ns or less) of a DRAM (Dynamic Random Access Memory), so that a counter enable signal (such as RCNT in FIG. 9(d)), which is abnormal, is generated.
On the other hand, when the enable period of the auto-refresh signal is excessively long, the auto-refresh signal and the counter enable signal may be simultaneously enabled during a low-speed operation (for example, tck=10 ns or more; ns=nano sec) carried out in, for example, a wafer test. In this case, there is a problem in that two different output internal row addresses GAX are output in one auto-refresh operation.